High performance integrated circuits utilize low K dielectric layers and copper metal to form the lines that interconnect the various electronic devices that comprise the circuit. The copper interconnect lines comprise copper formed in trenches and vias in the low K dielectric material.
Illustrated in FIG. 1 is a cross section diagram of a typical copper interconnect structure showing copper delamination. Copper delamination is a major problem that affects the reliability and operation of the integrated circuit. As shown in FIG. 1, a dielectric layer 10 is formed over a semiconductor. Electronic devices such as transistors, capacitors, and diodes will be formed in the semiconductor. In addition there may be any number of intervening layers and structures between the semiconductor and the dielectric layer 10. The semiconductor and any intervening layers have been omitted for clarity. A copper layer 20 is formed in the dielectric layer using known methods. A barrier layer 30 is formed on the copper layer and a second dielectric layer 40 is formed over the barrier layer. Using known methods such as the dual damascene method, copper lines 60 and vias 50, 51 are formed in the second dielectric layer. During subsequent processing various stresses will be formed in the copper interconnect structure. Currently this stress can lead to the delamination as shown in FIG. 1. As shown in the Figure, the copper via 51 has lifted away from the underlying copper layer 20 and is no longer making electrical contact with said layer. This lifting of the via from the underlying copper line is referred to as via delamination (or delamination). This delamination can cause the integrated circuit to become inoperable and fail. There is therefore a need for a method to form copper interconnect structures that will reduce and/or eliminate delamination. The instant invention addresses this need.